The present invention generally relates to semiconductor devices and more particularly to a lateral type semiconductor device having a plurality of diffusion regions of first and second conduction types along a top surface of a substrate.
In the so-called lateral type semiconductor devices such as a lateral pnp-transistor or resistors, a first diffusion region of a first conduction type and a second diffusion region of a second conduction type are formed alternately along the top surface of a substrate.
FIG. 1 shows a typical circuit diagram of such a lateral pnp-transistor in which the collector and the base are shorted to form a lateral pnp-diode. FIG. 2 shows a plan view of such a lateral pnp-diode formed on a substrate and FIG. 3 shows a cross-sectional view of the lateral pnp-diode of FIG. 2 taken along a line 3--3' of FIG. 2.
Referring to FIGS. 2 and 3, the lateral pnp-diode is formed within an n-type epitaxial layer 3 which is grown epitaxially on a p-type substrate 1. The n-type epitaxial layer 3 is formed with a plurality of isolation regions 4 repeated with a predetermined interval, and a lateral pnp-transistor forming the diode, is formed in a device region of the epitaxial layer 3 defined by a pair of such isolation regions 4. In correspondence to the device region thus defined, there is formed also a buried layer 2 of the n-type at a boundary between the substrate 1 and the epitaxial layer 3.
In the epitaxial layer 3, a p-type diffusion region 5 acting as the emitter of the lateral pnp-transistor is formed generally in correspondence to the central part of the device region, and another p-type diffusion region 6 acting as the collector is formed so as to surround the emitter region 5. Further, an n.sup.+ -type diffusion region 7 with an impurity concentration level exceeding the impurity concentration of the n-type epitaxial layer 3, is formed in a region of the epitaxial layer 3 outside the region surrounded by the collector 6 as a base contact region of the lateral pnp-transistor. This base contact region 7 contacts with the n-type epitaxial layer 3 which acts as the base of the pnp-transistor at a part of the layer 3 located between the emitter 5 and the collector 6. Further, an insulator layer 8 is provided on the epitaxial layer 3 so as to bury the emitter region 5, collector region 6 and the base contact region 7, and a collector conductor pattern 9 and an emitter conductor pattern 10 are provided on the insulator layer 8. It should be noted that the collector conductor pattern 9 is connected commonly to the collector region 6 and the base contact region 7, and thus, the lateral pnp-transistor forms a lateral pnp-diode having the circuit diagram shown in FIG. 1. On the other hand, the emitter conductor pattern 10 crosses the collector region 6 at a level above the level of the collector region 6.
In such a pnp-lateral diode, there occurs a problem such that parasitic MOS transistors are formed between the p-type isolation region 4 acting as a source and the p-type collector region 6 acting as a drain with the intervening epitaxial region 3 acting as the channel region, and further between the p-type collector region 6 acting as a drain and the emitter region 5 acting as a source with the intervening epitaxial region 3 acting as the channel region as shown in FIG. 3. In any of these parasitic MOS transistors, the insulator layer 8 acts as the gate oxide film and the collector conductor pattern 10 acts as the gate electrode.
FIG. 4 shows an equivalent circuit diagram of the structure of FIG. 3 including these parasitic MOS transistors. As can be seen in the equivalent circuit diagram, the parasitic transistors form a single MOS transistor 11 of multiple source construction. This parasitic MOS transistor 11 of FIG. 4 operates as an enhancement mode MOS transistor and is turned on when the voltage level at the collector conductor pattern 9 and thus the voltage level at the collector region 6 has exceeded the voltage level of the emitter region 5 by a threshold voltage pertinent to the MOS transistor 11. In other words, when the lateral pnp-diode is biased in the reverse direction with a reverse voltage level exceeding the threshold voltage of the parasitic MOS transistor 11, a leak current flows from the collector region 6 to the isolation region 4 and further from the collector region 6 to the emitter 5 and thus, the lateral pnp-diode causes a breakdown.
In order to avoid this problem of poor breakdown characteristic, there is a proposal to provide an n.sup.+ -type diffusion region 12 between the collector region 6 and the p-type isolation region 4 with an increased impurity concentration level as shown in FIG. 5. The n.sup.+ -type diffusion region 12 thus provided interrupts the flow of holes through the channel region between the source region 4 and the drain region 5, and the formation of the parasitic MOS transistor in this region is substantially eliminated.
However, this approach to eliminate the parasitic MOS transistor is incomplete, as only one of the MOS transistors forming the parasitic MOS transistor 11 is eliminated while the other of the MOS transistors forming the MOS transistor 11 is left as it is without any change between the collector region 6 and the emitter region 5. The provision of a doped region between the collector region 6 and the emitter region 5 similarly to the doped region 12 would cause a disastrous result in the performance of the bipolar transistor, as this region between the collector region 6 and the emitter region 5 is used for the base of the pnp-transistor and is critical to the operational characteristic of the transistor.
Further, such a provision of the additional diffusion region is undesirable from the view point of increasing the integration density and hence the operational speed of the device. It is needless to say that the provision of another doped region similar to the region 12 between the collector region 6 and the emitter region 5 causes an unnecessary increase of the size of the semiconductor device.